Interconnection Architecture model of the Architecture Configuration Stream Configurable Inputs

Most reconngurable multi-fpga architectures have a programmable interconnection network that can be reconngured to implement diierent interconnection patterns between the fpgas and memory devices on the board. Partitioning tools for such architectures must produce the necessary pin-assignments and interconnect connguration stream that correctly implement the partitioned design. We call this process Interconnect Synthesis for reconngurable architectures. In this paper, we present an interconnection synthesis technique that is independent of the target reconng-urable architecture. We have developed an automatic interconnect synthesis tool that is based on Boolean satissability. The target interconnection architecture is modeled in an architecture speciication language. The desired interconnections among the fpgas are speciied as in the form of a netlist. The tool automatically generates the pin-assignments and the required values for the connguration-inputs in the architecture speciication. We modeled several reconngurable architectures and performed interconnect synthesis for varying number of desired nets. We provide experimental results that demonstrate the eeectiveness of the interconnection synthesis technique.